Variance mismatch: identifying random-test resistance in DSP datapaths

Abstract

Pseudorandom built-in self-test (BIST) is an attractive means of testing DSP datapath structures as long as the delay and area overhead can be kept low. One obstacle to low-overhead BIST is random-pattern test-resistant datapath structures. We examine the causes of this resistance in some typical DSP datapaths, and introduce variance mismatch as an analytical tool for identifying these test problems. By understanding the mechanisms behind random-pattern test resistance, it is possible to make design decisions that are compatible with pseudorandom BIST, resulting in reduced test length and higher fault coverage. Variance matching theory is applied to the design of two large FIR filters, resulting in an 88% reduction in the number of missed faults for a fixed test length, and two orders-of-magnitude reduction in test length for a specific fault coverage target.