Abstract

Slotted WDM rings are considered to implement high-speed all-optical metro networks. The usual approach to transfer variable-size data units, such as IP data-grams, is to segment them into cells, and transfer each cell independently in the WDM ring. This approach entails complexity due to segmentation/reassembly procedures. We investigate in this paper architectures and control strategies to guarantee that all segments of a variable-size packet are sent contiguously on the ring, thereby drastically reducing reassembly complexity. Our proposal is based on register insertion techniques exploiting optical delay lines. A number of schemes are proposed, and compared by means of simulation, showing how performance impairments can be traded with hardware complexity.KeywordsMedium Access ControlDelay LineMedium Access Control ProtocolRing NetworkEmpty SlotThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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