Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic

Abstract

A new variable strength keeper technique is proposed in this paper for achieving robust, high-speed, and low-leakage dynamic logic gates with carbon nanotube transistors. The strength of keeper is dynamically adjusted depending on the logical state of dynamic node during input evaluation phase in a domino logic circuit. While providing similar noise immunity, the evaluation delay and power-delay product of proposed domino circuits are reduced by up to 13.33% and 13.84%, respectively, as compared to standard domino circuits in a 16nm carbon nanotube transistor technology. Furthermore, the proposed domino circuits provide up to 77.98% savings in average leakage power consumption as compared to standard domino logic circuits in idle mode.