Variable frequency clock study using DSL/VS

Abstract

A variable frequency clock (VFC) is an example of a common electronic feedback control system that defies rigorous analysis yet is readily studied by time domain simulation. Composed of several nonlinear as well as linear blocks, continuous and discrete elements, feedback and feedforward paths, such systems are also subject to input and parameter variations of stochastic nature. They are typically conceived by inventive engineers without the benefit of much analysis. Simulating such circuits by representing each component is possible but often unwieldy and of little help to the designer at inception. But, with the help of IBM's Dynamic Simulation Language (DSL/VS), a higher level model is easily coded, rapidly computed and conveniently evaluated by inspection of graphs. This permits accurate performance prediction as well as design optimization with or without man in the loop. A specific clocking scheme, employed in several IBM tape drives, is used as an example of modeling and simulating a hybrid circuit. Block and timing diagrams, complete application program code, and some graphs are given for this sample problem.