Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units

Abstract

Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-and-Accumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.