Abstract

The random variation sources have a significant influence on the performance of ferroelectric field-effect transistor (FeFET). In this work, comparative analysis on the process variation induced variability of FeFET towards a 7 nm technology node has been conducted, including different device structures from bulk to FDSOI and FinFET. The random ferroelectric/dielectric phase variation (PV), the metal work function variation (WFV) and the line-edge roughness (LER) effects are incorporated in TCAD simulations to quantitatively investigate their impacts on the threshold voltage variation. Especially, the Voronoi diagram is employed to realistically model the ferroelectric grain distributions and to accurately simulate the impact of PV on FeFET characteristics.

Highlights

  • Ferroelectric materials have been studied for next-generation nonvolatile memory devices because they possess electrically controllable spontaneous polarization states [1], [2]

  • Since the gate line-edge roughness (LER) does not affect the device performance significantly for the bulk field-effect transistor (FeFET) compared to the work function variation (WFV) and phase variation (PV) [12], it is not included for bulk FeFET simulation

  • As an initial estimation, Fig. 5 shows the high Vth (HVT) and low Vth (LVT) distribution of a generic bulk FeFET depending on the grain size with 100 samples

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Summary

Introduction

Ferroelectric materials have been studied for next-generation nonvolatile memory devices because they possess electrically controllable spontaneous polarization states [1], [2]. Ferroelectric materials having perovskite structure such as lead zirconium titanate (PZT), barium titanate (BTO) or strontium bismuth tantalite (SBT) have been used for FeFET [4]. Those materials need to be thick (at least 100 nm) to exhibit ferroelectric properties, which becomes the limitation to scale down the FeFET to advanced technology node. The Hafnia based ferroelectric materials have received a lot of attentions since only few-nm could achieve the ferroelectric properties They are compatible to the silicon CMOS fabrication processes using atomic-layer deposition (ALD) [4]

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