Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power

Abstract

In this paper, we present an accurate and efficient stack based macromodel for statistical subthreshold leakage power characterization of cmos gates. Our methodology is based on first characterizing the leakage power of basic stacks and then estimating the subthreshold leakage power of gates based on these stacks. We develop support vector machine (SVM) based macromodels to characterize the transistor stacks of cmos gates, while accounting the combined effect of process variation in length (L), threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ), supply voltage (0.6v-1.2v), temperature (0°C-100°C) and width (45nm-200nm) scalable at the same time. Our experiments show that we only need 30 stack models to predict the subthreshold leakage power of 7 basic gates across 58 input combinations. SVM based models have the ability to predict the leakage power with maximum average error of less than 0.634% in mean for 4 input NOR gate and maximum average error of 1.952% in standard deviation for 3 input NOR gate. Our results also show that there is on the average 17× improvement in runtime for estimating the mean and standard deviation of leakage power of a gate with 5000 Monte Carlo simulations.