Validation-Based Test Sequence Generation for Networks of Extended Finite State Machines

Abstract

We describe a method for the automatic generation of test sequences that has been implemented as part of the Virtual Finite State Machine (VFSM) toolset. VFSM has been used extensively in software development for the Lucent Technologies 5ESS® switching system. The method produces a set of sequences of messages which, when provided as input to a VFSM, result in nearly complete code coverage. The method relies on information collected by the VFSM validation tool, which uses Holzmann’s supertrace algorithm to explore execution scenarios of a network of VFSMs and search for errors such as deadlock and unexpected inputs. We have applied our method for the generation of test sequences to a VFSM implementation of the ETSI Intelligent Network Application Protocol (INAP). Because of the large size of INAP, we were unable to validate it completely due to state explosion arising from the exhaustive search that the VFSM validator performs. We therefore devised a novel partial validation technique that attempts to generate a subset of the state space of a network of VFSMs and derives test sequences that maximize the code coverage and minimize the number of tests. In this paper, we present an overview of our test-sequence-generation method and its application to the VFSM implementation of NAP.