Validating the itanium 2 exception control unit: a unit-level approach

Abstract

Each new microprocessor endeavor strives to achieve the performance gains projected by Moore's law. Such performance arises, in part, from innovative and often from complex microarchitectural features. This trend of increasing functional complexity has already exacerbated the challenge of design validation, making validation the critical path to tapeout. Traditional approaches to functional validation include both focused case writing and the development of random-code generators. In either case, this method is limited to engineering thought experiments - the human mind can only process a finite set of states in a seemingly infinite machine state space. In April 2000, the functional model for the Itanium 2 design was nearing tape-out quality. Engineers had written most focused cases to satisfy test plan goals; the random-code generators were mature and pounding away at the RTL model with no restrictions; and the bug rate was steadily decreasing for most units. Despite this encouraging trend, engineers were still concerned with the functional quality of the exception control unit (XPN), one of the most control-logic-intensive units on the chip.