Validating a DFT Strategy’s Detection Capability regarding Emerging Faults in RRAMs

Abstract

Over the last fifty years, Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down according to the predictions made by Gordon Moore in the 1960s, hence making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints in terms of size, power consumption, and response latency. Thus, memristive devices have become promising candidates to complement or replace the CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability and density, as well as their capability to implement high-density memories as well as new computing paradigms. Despite these advantages, memristive devices are also suscreptible to manufacturing defects that may cause faulty behaviors not observed in CMOS, significantly increasing the test complexity. This paper presents the validation of a Design-for-Testability (DFT) strategy for Resistive Random Access Memories (RRAMs). The proposed strategy, able to detect traditional and unique faults in RRAM cells, has been implemented using an X-Fab technology library and validated based on a simplified case study. The obtained results show that the idea of applying a predefined operating sequence in combination with electrical measurements can guarantee the detection of unique faults in RRAM cells.