Utilizing logic information in multi-level timing simulation

Abstract

Multi-level simulation arith a dynamic model level selection mechanism is a technique for increasing simulation efficiency. Implementation considerations dictate a pessimistic dynamic model selection mechanjsm which could rault in longer execution times than a normal simulation of a flattened logic network. Om equivalence class concept lessens the impact of the pessimistic xlection mechanism by detecting currently dormant logic blocka with reaped to an input transition. Earlier work on timing simulation incorporated multiple model levels with a dynamic model level selection mechanism[l]. Similar multiple model level approaches have revealed comparable execution increases of three to five times over that of simulation using the lowest model levels[lO]. Unfortunately, due to practical limitations, the dynamic model selection mechanism is more pessimistic than necessary and results in an appreciable performance degradation due to the unnecessary invocation of lower model levels. In this work, we describe a technique to lessen the impact of the pessimistic dynamic model selection mechanism. Our technique called equivalence classes is based on anticipating a subcircuit block’s output activityin response to a transition at the block’s input node. We fmt start with the description of our simulation environment and then describe OUT equivalence classes concept. We continue with presentation of algorithms to extract equivalence classes from gate level logic descriptions, present implementation details and results, and finally our conclusions.