UTBB SOI MOSFETs with gate-source/drain underlap and ground plane (GP) structures for analog/RF applications

Abstract

In this work, we report on the influence of underlap architecture (L UL ) and ground plane (GP) on the analog/RF performance metrics of Ultra-Thin Body and Buried Oxide (UTBB) Fully-Depleted (FD) SOI MOSFETs with 25 nm gate length. Small-signal transconductance (g m ), gate-to-gate capacitance (C gg ) and the cut-off frequency (f t ) are the figures-of-merit (FoM) of interest. It is shown that longer underlap i.e. L UL = 10 nm showed lower g m . However, it is noted that C gg also decreases as the underlap increases. Thus, the need for trade-off between g m and C gg is needed to achieve optimum values of f t . From this work, it is found that the impact of g m on f t is more prominent than C gg . From another point of view, the impact of different GP structures on g m and f t becomes more apparent at longer underlap.