Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration

Abstract

Multi-FPGA prototyping, because of its low cost, high speed, and real world testing is quite popular today for pre-silicon verification of increasingly complex designs. In this work, we present a novel exploration flow that is used to analyze and optimize the multi-FPGA based prototyping of complex digital designs. In this flow, an end-to-end experience starting from benchmark generation to optimized inter-FPGA routing is given. For inter-FPGA routing, timing-driven approach is used instead of previously used routability-driven approach. Ten large designs are generated using generic tools of the flow and then effect of number of FPGAs on board, number of inter-FPGA tracks is observed on the performance of generated designs. Extensive experimentation reveals that FPGA board with six FPGAs gives best system frequency results. Furthermore, execution time comparison between routability and timing-driven approach reveals that compared to routability-driven approach, timing-driven approach consumes, on average, 46% less time while giving same or better frequency results.