Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory

Abstract

Because of its great scalability potential and support of multi-level per cell storage, phase change memory has become a topic of great current interest. However, recent studies show that structural relaxation effect makes the resistance of phase change material drift over the time, which can severely degrade multi-level phase change memory storage reliability. This paper studies the potential of using a time-aware memory sensing strategy to address this challenge. The basic idea is to keep track of memory content lifetime and, when memory is being read, accordingly adjust the memory sensing configuration to minimize the negative impact of time-dependent resistance drift on memory storage reliability. Because multi-level phase change memory may demand the use of powerful error correction code (ECC) whose decoding can request either hard-decision or soft-decision log-likelihood (LLR) memory sensing, we discuss both hard-decision and soft-decision time-aware memory sensing in details. Using BCH code and LDPC code as ECC for 4-level/cell and 8-level/cell phase change memory, we carry out simulations and the results show that, compared with time-independent static memory sensing, time-aware memory sensing can increase allowable memory content lifetime by several orders of magnitude.