Abstract
Semiconductor manufacturing and technology testing are developing at different speeds, and yield loss due to inaccuracies in the testing process has become an important issue. The integrated circuit test model is applied in this study using an iterative yield prediction method (IYP) to estimate the fabrication yield of future wafers based on their process parameters and electrical characteristics. Additionally, test guardband estimation (TGE) method is proposed to adjust the test guardband to maintain the desired product quality after testing. The proposed iterative yield prediction method is demonstrated using a set of parameters from the IEEE International Roadmap for Devices and Systems (IRDS) 2021. Evaluation of the specifications in the IRDS table reveal shows that IYP can demonstrate the appropriate yield curve as predicted.
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