Using the MSET Device to Counteract Power-Analysis Attacks

Assaf Peled,Ofer Amrani,Yossi Rosenwaks,Avishai Wool,Liron David

doi:10.1109/jeds.2020.3032635

Assaf Peled, Ofer Amrani + Show 3 more

Open Access

https://doi.org/10.1109/jeds.2020.3032635

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Abstract

One pivotal countermeasure in dealing with side-channel power analysis attacks is to maintain the signal-to-noise ratio of the power readings associated with the target as data-independent and as low as possible, in order to limit the attacker's ability to deduce meaningful information from the target. The following study shows that the MSET (Multiple-State Electrostatically-Formed Nanowire Transistor) device achieves these two desired outcomes by virtue of its low-power characteristics, therefore having an inherent advantage in terms of side channel attacks over prevalent technologies. This advantage is tested with an SRAM cell and a memory register. Using correlation metrics, the correlation coefficient of the Hamming distance to the power dissipation in the register - at the adversary's point of observation - is shown to be close to zero over multiple power traces, when the register is implemented in MSET technology.

Highlights

THE combined capabilities of the MSET (Multistate Electrostatically-Formed Nanowire Transistor) design and unconventional operation have been subject to recent studies[1][4] which demonstrated the MSET’s pronounced benefits at low-power and low-voltage in a variety of applications
If the adversary assumes that the power consumption at the point of observation in either technology depends on the switching activity during computation, the Hamming distance model can serve well to predict the leakage as measured on the test resistor in a correlation power attack
Our analysis shows that the power measured at the point of observation of the adversary has near constant value in the MSET case, irrespective of the switching activities performed

Summary

INTRODUCTION

THE combined capabilities of the MSET (Multistate Electrostatically-Formed Nanowire Transistor) design and unconventional operation have been subject to recent studies[1][4] which demonstrated the MSET’s pronounced benefits at low-power and low-voltage in a variety of applications. The power consumption of the cell, or a register for that matter, can be monitored by inserting a small resistor within the supply chain, e.g., below the lower-end supply rail of the integrated circuit target device Acquisition tools such as multi-channel oscilloscope normally accompany this type of attacks, and a computer is used to conduct statistical analysis on the PAA traces. The only current measureable is the short circuit path to the ground rail This data-dependent power consumption distinguishes the side-channel information leakage in the FDSOI case.

TABLE II

CONCLUSION

Paradigm for Integrated Circuits Based on the MSET

Power Performance of Multiple State Electrostatically

Methodology for a Secure DPA Resistant ASIC and FPGA