Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAs

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) endured a considerable evolution in the last few years, both in terms of density and complexity, with nanometre technology being currently used in their manufacturing. However, the exponential growth of the number of memory cells needed for configuration purposes makes them especially vulnerable to radiation induced faults, like Single Event Upsets (SEU), even at ground level [1–3]. These faults can permanently degrade the performance or change the functionality of the circuit implemented on the FPGA in different ways, namely: (1) by changing the routing configuration; by modifying the contents of the (2) Look-Up Tables (LUT) or (3) dedicated memory blocks; and (4) by inverting the contents of the flip-flops located at the Configurable Logic Blocks (CLB) and the Input/Output (I/O) blocks. At this point we should distinguish between resources that are being (A) used and (B) not used. We propose an online mechanism capable of detecting all possible bit-flips in some of the resources not being used, namely 1B, 2B, and 3B parts, and also on some of those being used, namely 1A, as this information is static after the FPGA configuration process. Any bit-flip on an FPGA flip-flop, i.e. 4A and 4B parts will not be detected through the configuration memory. The information contained in the LUTs and dedicated memory blocks in use can be static or dynamic depending of the circuit implementation and functionality. Bit-flips occurring in 2A-static and 3A-static parts can also be detected depending on the architecture of the FPGA under evaluation. For instance, in FPGAs from the Virtex-II family, the contents of the configuration memory are accessed on a frame-per-frame basis. If a frame contains elements pertaining to 2A-dynamic and 3A-dynamic parts then this frame should not be read so as to avoid corrupting the contents of such dynamic parts [4]. This implies not being able to access the bit contents of all the other static parts addressable through that very same frame. Information about the FPGA configuration memory organization is usually provided by the manufacturer or, in its absence, it is still possible to extract structural information using methods reported in literature [5].