Using Pruning and Truncation for Power-Efficient 2-D Approximate Tchebichef Transform Hardware Architecture

Abstract

Due to the intensive use of discrete transforms in pic-ture coding, the search for fast and power-efficient approaches for their hardware implementation has gained importance. The DTT (Discrete Tchebichef Transform) represents a discrete class of the Chebyshev orthogonal polynomials, and it is an al-ternative for the DCT (Discrete Cosine Transform), commonly used in picture coding. In this work, we propose a new approx-imation for the integer DTT, with better quality and power-ef-ficiency by exploring truncation and pruning. The principal idea is reduce the values of coefficients to fractions enables trun-cation by shifts in the internal transform calculations and lead to lower values for the non-diagonal residues, which reduces non-orthogonality. We have also selectively pruned the rows of the state-of-the-art approximate DTT matrix. The approximate DTT architectures were synthesized for ASIC in Cadence RTL Compiler tool using a realistic power extraction methodology considering real-inputs vectors and the delays, with the Nangate 45 nm standard cells library. The synthesis results show that the proposed-pruned approximate DTT hardwired solution in-creases the maximum frequency about 10.78%, minimize cells area by 50.2%, with savings up to 55.9% of power dissipation with more compression ratio and less quality losses in the com-pressed image, when compared with state-of-the-art approxi-mate DTT hardware designs.