Using on-chip test pattern compression for full scan SoC designs

Abstract

In todays mixed signal System-on-Chip designs advanced Design-for-Test techniques become more and more important to meet test coverage and quality requirements. However, standard strategies often cannot be used because of design specific requirements like the limitation of available input and output pins. This paper describes the Design-for-Test strategy of the latest version of Motorola's chip family for a mixed signal application. Deterministic test pattern, which are generated using an ATPG tool, have been used to stimulate the design and achieve efficient and high test coverage. The memories are tested by using a memory BIST implementation. The limitation of available digital input and output pins is solved in two ways. Analog input pins have been modified to serve as digital pins in test mode. On-chip test pattern compression using a multiple input shift register (MISR) is used to reduce the number of required output pins. Failure diagnostic capabilities have been implemented to allow debug of failing devices. The paper describes the test strategy for the System-on-Chip device and outlines the design flow which was used to implement it.