Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designs

Abstract

Functional verification of data dominated high-level designs is a major concern in modern integrated circuit production flow. On the one hand, the size and complexity of the input state-space prevent conventional validation strategies to check the behaviour of the design thoroughly using simulation. On the other hand, formal verification methods still face difficulties while verifying high-level designs, specially when complex data types and dynamically allocated data structures are used. This work presents a method based on guiding heuristics for dynamically checking temporal properties of high-level designs. The properties are translated into heuristic functions that are combined with the black-box model of the system in order to guide the validation effort to error prone regions of the design's input domain. The functions are designed in a way that their minimum points correspond to properties violations, if they exist. Optimization algorithms are used to evaluate the property under check by searching for input sequences that minimize the heuristic functions. Experiments indicate a significant improvement in the efficiency of the verification process when the proposed method is used, with respect to both random simulation and bounded model checking.