Using e-Beam inspection and overlay as tool for identifying process weaknesses in semiconductor processing

Abstract

Shrinking design rule coupled with complex device geometries and introduction of new materials in the manufacturing of today’s semiconductor devices generate inherent device weak points which in turn give rise to mechanisms that result in yield impacting defects. The development and introduction of finFET has helped considerably in the quest to further shrink design rule. However, the design and complex manufacturing process involved in producing these high performance finFET devices bring with it a whole new class of defects that have considerable impact on device performance and yield. Some of these defects are buried beneath the wafer surface and are very difficult to detect. They are often missed by optical inspection, only to cause fails at final testing. Failure analysis (FA) then becomes the only means by which they are uncovered. FA is a destructive methodology and its benefits are realized only after the fact. Unlike FA, e-Beam inspection is non-destructive. e-Beam uses electron optics and has a unique ability to detect buried defects electrically by voltage contrast (VC) between a defective structure and its reference. As process window gets tighter and tighter process margin becomes difficult to predict. In this work, e-Beam inspection and overlay data is used to identify process weakness regions on wafer to predict fails and help optimize process and improve yield.