Using defect density modelling to drive the optimisation of circuit layout, maximising yield

Abstract

With integrated circuit [IC] market requirements driving the increase in diversity of product families and technologies, modelling of defect density within wafer fabrication is increasing in complexity. The exponential growth in the number of applications of the IC has meant that the requirement of each wafer fabrication facility has moved from running single volume products to being able to cope with running up to hundreds of different products at one time. Where it is possible to retain one volume product per wafer fabrication site, simpler defect density modelling may be representative models or indicators of defect density. When multiple process flows, product families and technologies are manufactured at one time, using one model was found to be unviable. By developing wafer fabrication site specific models, the effects of inline defectivity and design layout were found to consistently relate to yield. Product family variations also showed relationships with yield, where memory size, complexity and module choice could be optimised to maximise yield of a new product.