Abstract
AbstractAs a solution to improve the characteristics of pseudo‐random pattern tests, a BIST‐oriented test pattern generator (TPG) designed to achieve complete coverage of stuck‐at faults with short test sequences is proposed. In the proposed method, ATPG vector sets are split‐shifted to obtain pseudo‐random vectors, and such vectors are then used in a mixed test pattern. Since random pattern resistant faults are detected by ATPG vectors, stuck‐at faults can be covered completely with a short test sequence. This paper presents the proposed TPG configuration, test pattern generation algorithm, and the selection of the vector set for bit shift. The proposed method is evaluated in terms of test length and hardware overhead by applying it to ISCAS benchmark circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(11): 1–8, 2001
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