Abstract

This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Tchebichef Transform (DTT) implementation. Due to the huge use of the discrete transforms in image compression, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DTT represents a discrete class of the Chebyshev polynomials, and it is an alternative for the common DCT (Discrete Cosine Transform), which is present in several compression systems. High energy compaction and decorrelation are indicated as main properties of this transform. The approximate DTT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. As the resultant matrix of the state-of-the-art approximate DTT presents only 0, 1, −1, 2, and −2 values, thus it can be easily implemented in hardware using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2, 6-2, and 8-2 adder compressors for the state-of-the approximate DTT implementations. We present an environment for the synthesis of the DTT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DTT solutions, with adder compressors, minimizes both cells area and power dissipation, when compared with the native DCT.

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