Using a genetic algorithm approach to reduce register file pressure during instruction scheduling

Abstract

Instruction scheduling and register allocation for VLIW architectures are complex problems for which computing the optimal solution is often infeasible. Instead, optimization techniques and heuristics are used to find good solutions in reasonable time. List scheduling is a well known microcode compaction method, which uses weights derived from data dependency graphs of the input program in its heuristic function. Additional information and mechanisms have to be used in order to reach better code compaction. In this paper, a genetic algorithm is used to tune the heuristics during list scheduling, which allows dynamic adaption of the algorithm to the given input program. The genetic scheduler often outperforms list scheduling with static heuristic and handles situations with register file pressure that might be impossible to schedule with the heuristic based list scheduling. A second genetic algorithm is proposed to perform X2 operation merging, a code optimization step exploiting special execution mode of the target hardware architecture.