Use of simulated annealing to reduce 2-bit decoder PLAs

Abstract

A 2-bit decoder programmable logic array (PLA) is an array of transistors that realizes the sum of products (realized by rows of transistors) of inputs taken from the outputs of 2-input 4-output decoders. Functions of several variables, which are assigned to the decoder inputs using Tomczuk and Miller's heuristic algorithm to pair closely related variables using the autocorrelation of the functions, are realized using reduced area PLAs. The number of product rows (representing product terms) used in such PLAs, which is a function of the assignment of pairs of variables to the decoders, is reduced using simulated annealing techniques which are applied to permuting the assignment of input variables to the decoder inputs.