Use of constraint solving in order to generate test vectors for behavioral validation

Abstract

Validation of VHDL descriptions at the early phases of the microelectronic design is one of the most time consuming task design. This paper presents a test vector generation method for behavioral VHDL design. This method analyzes control and dependence flow of VHDL program. We use the cyclomatic complexity, that is a software metric based on a graph associated with the control part of software: the control flow graph (CFG). Significant control flow paths are selected using a powerful algorithm: the Poole's algorithm. The execution of this set of paths satisfies the coverage of each decision outcome of the VHDL program. Any additional test path would be a linear combination of the basis paths already tested and therefore considered to be redundant. By considering the selected paths as a group of constraints, test data are generated and solved using constraint programming. These data form the test bench that test the VHDL description.