Use of CMOS Technology in Wave Pipelining

Abstract

Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. This is achieved by clocking the system faster than the propagation delay between storage elements. The design of such sys- tems is more difficult because all paths in the combinational logic must have about equal delay. To implement wave pipelining, some technolo- gies seem to be better than others depending on the delay properties. Static CMOS has the disadvantage of pattern-dependent delay variations. This papers discusses the issues concerning the implementation of wave pipelining using CMOS technology. The maximum pipeline rate for a wave-pipelined circuit is calculated under data-dependent delay con- straints. Bounding parameters to the system performance are provided.