Updates of nanoimprint lithography for production and applications for next generation memory devices

Abstract

In order to significantly reduce investment cost in lithography, nano imprint lithography (NIL) technology has aggressively been developed. Over the past few years, Toshiba, with the support of Canon and DNP, has developed NIL technology for the application of advanced memory devices and succeeded in yielding working devices at dimensions less than sub 20nm and beyond. A production tool in a mask house for template and NZ2 in Si fab were installed and ready for production. The pattern shrinkage for memory has just restarted for new memory such as storage class memory called SCM. The SADP and SAQP ArF multi-patterning with a spacer process may not be applied to the next-generation memory process due to thermal problems in semiconductor materials. Low-cost single exposure with NIL will be an ideal process. All exposure tools should be considered for extendability across different device nodes as an economical strategy. The next application of NIL will be extend from contact hole and dense pattern without multi patterning to 3D pattering such like damascene process and to outside of semiconductor devices. In this paper, the status of the nano imprint lithography for high volume manufacturing is discussed, along with key challenges that must be addressed. Moreover, proprietary technology of NIL such as 3D and wide field patterning is discussed.