Unified TDDB model for stacked high-k dielectrics

Abstract

Time dependent dielectric breakdown (TDDB) characteristics of high-k dielectric have been intensively studied, but the validity of various approaches to interpret TDDB characteristics has not been rigorously reviewed. Diversity of gate stack structures and integration processes are parts of reasons why it is difficult to come up with a consistent model to explain the reliability data. In some cases, the quality of metal/high-k stacks is simply not good enough to study the intrinsic properties of the material systems and very limited research group has an access to such devices as the gate stack process and its quality is so closely tied with actual products and integration path. Also, TDDB test methodology itself can be a problem. Many reliability test methods developed for SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric have been used without a close examination. For example, comparison between a conventional constant voltage stress and a constant current stress, a pulsed stress and an alternating bias stress, a high field stress and low field stress have not been performed. In this paper, various aspects of TDDB models proposed for high-k dielectrics are reviewed and a unified model that can resolve major discrepancies among those models is proposed.