Unified physical I- V model of fully depleted SOI/MOSFETs for analog/digital circuit simulation

Abstract

An improved physical I- V model for fully depleted SOI/MOSFETs with channel lengths down to deep submicrometer range is presented. The model contains the following advanced features: precise description of the subthreshold, near-threshold and above-threshold regimes of operation using one single expression; precise description of I- V and G- V characteristics in the saturation region; continuous and smooth transition of the drain current and conductance from the linear to the saturation regime; extrinsic model expressions for devices with parasitic drain and source series resistances; inclusion of important short channel effects accounting for velocity saturation, drain induced barrier lowering (DIBL) and drain induced conductivity enhancement (DICE), channel length modulation (CLM), as well as the gate bias dependent mobility; a description of the floating body effect associated with drain breakdown. Inclusion of these features greatly improves the accuracy as well as the convergence properties and the calculating efficiency when using the model in circuit simulators. The present model agrees well with experimental results for a wide range of process and device parameters.