Abstract
Field Programmable Gate Arrays (FPGAs) are increasingly being used to implement large datapath-oriented application that are designed to process multiple-bit wide data. Studies have shown that the regularity of these multi-bit signals can be effectively exploited to reduce the implementation area of datapath circuits on FPGAs that employ the traditional bidirectional routing. Most of modern FPGAs, however, employ unidirectional routing tracks which are more area and delay efficient. No study has investigated the design of multi-bit routing resources that can effectively transport multiple-bit wide signals using unidirectional routing tracks. This paper presents such an investigation of architectures which employ multi-bit connections and unidirectional routing resources to exploit datapath regularity. It is experimentally shown that unidirectional multi-bit architectures are 8.6% more area efficient than the conventional architecture. Additionally, this paper determines the most are efficient proportion of multi-bit connections.
Highlights
The rate at which the temperature is reduced and the number of moves attempt at each set temperature value is defined in the annealing schedule.Virtual Place and Route (VPR) uses an adaptive annealing schedule, which adapts to a wide range of Field Programmable Gate Arrays (FPGAs) architectures, cost functions and circuit sizes [7] while consuming a reasonable amount of computation time
This study has explored the effect on FPGA area efficiency of multi-bit connections using unidirectional routing in order to efficiently implement arithmetic intensive circuits
In order to accommodate the use of non-ideal signals in modern circuits, pairs of singular signals are added to the routing buses to form the unidirectional multi-bit routing architecture
Summary
The motivation of this thesis centres on investigating how using multi-bit based connections on unidirectional routing resources affect FPGA area efficiency. In this research we determine the theoretical area savings of a purely routing bus-based FPGA tile over that of a conventional tile; both of which employ unidirectional routing. We introduce the multi-bit architecture which employs both bus-based and singular unidirectional routing elements. In practical FPGAs, architectural aspects such as channel width and I/O connectivity are pre-fabricated and the goal of this research is to determine a suitable architecture to efficiently implement datapathoriented applications. Previous studies [11] [12] [13] [14] [15] have proposed various FPGA architectures containing specialized computing elements that are designed to process multiple-bit wide data. None of the studies have investigated the design of multi-bit routing resources that can effectively transport multiple-bit wide signals using unidirectional routing tracks
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