Abstract

For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, ultra-shallow and abrupt profiles. In the case of p-type (boron) implants, one method to achieve this is using Ge preamorphization (PAI) prior to ultra-low energy B implantation. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Understanding the strong impact of the buried Si/SiO 2 interface, will enable tests of fundamental models on defect evolution, electrical activation and diffusion. In the present study, boron has been implanted in germanium-preamorphized silicon and SOI wafers. Subsequent to implantation, an isochronal and isothermal annealing study of the samples was carried out. Electrical and structural properties were measured by Hall effect and SIMS techniques. The results show a range of effects in both substrate types, including TED and deactivation driven by interstitials from the end-of-range (EOR) defects. However, in the SOI material there is a lower boron deactivation and the EOR defects are eliminated at a lower thermal budget in SOI than in the bulk silicon due to competition between the upper SOI interface and the Si surface which both act as sinks for interstitials.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.