Abstract

Ferroelectric technology is becoming ever more appealing for a variety of applications, especially analog neuromorphic computing. In this respect, elucidating the physical mechanisms occurring during device operation is of key importance to improve the reliability of ferroelectric devices. In this work, we investigate ferroelectric tunnel junctions (FTJs) consisting of a ferroelectric hafnium zirconium oxide (HZO) layer and an alumina (Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> ) layer by means of C-f and G-f measurements performed at multiple voltages and temperatures. For a dependable interpretation of the results, a new small signal model is introduced that goes beyond the state of the art by i) separating the role of the leakage in the two layers; ii) including the significant impact of the series impedance (that depends on the samples layout); iii) including the frequency dependence of the dielectric permittivity; iv) accounting for the fact that likely not the whole HZO volume crystallizes in the orthorhombic ferroelectric phase. The model correctly reproduces measurements taken on different devices in different conditions. Results highlight that the typical estimation method for interface trap density may be misleading.

Highlights

  • The need to develop energy-efficient circuits for artificial intelligence applications running on edge devices leading the exploration of innovative solutions

  • For a dependable interpretation of the results, a new small signal model is introduced that goes beyond the state of the art by i) separating the role of the leakage in the two layers; ii) including the significant impact of the series impedance; iii) including the frequency dependence of the dielectric permittivity; iv) accounting for the fact that likely not the whole HZO volume crystallizes in the orthorhombic ferroelectric phase

  • Differences in at strongly negative bias can be attributed to different low frequency leakages, due to different devices states

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Summary

Introduction

The need to develop energy-efficient circuits for artificial intelligence applications running on edge devices leading the exploration of innovative solutions. The hafnium zirconium oxide (HZO)-based Ferroelectric Tunnel Junctions (FTJs) with Metal/Insulator/Ferroelectric/Metal (MIFM) structure are promising candidates to act as synaptic elements in analog neuromorphic architectures [2]. In this respect, achieving functional circuits requires a satisfactorily large compensation of the polarization charges, that is instrumental to the a) b) c) d). C-f/G-f measurements (Fig. 1b) are carried out at different DC voltages (-4.5 V to 4.5 V for =2/2.5nm and 4V to 4V for =1.5nm), temperatures (30°C to 100°C), and frequencies (up to 10 MHz) The latter is an important novelty, since existing works do not explore the range above 1 MHz [2,3]. The admittance of the entire stack is measured as the parallel of a capacitance (Cp) and a conductance (Gp), Fig. 1c, and includes the contribution of the AD and of layout c)

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