Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic

Abstract

In this paper, the impact of intradie process variations on the delay of nanometer Domino logic is investigated. Analysis shows that Domino logic circuits suffer from a 2X higher variability compared to static CMOS logic, which translates into a greater speed penalty. The main variability sources of Domino gates at the circuit level are identified and analyzed by means of simple circuit models and Monte Carlo simulations on a 90 nm CMOS technology. The role positive feedback in Domino gates is also discussed in depth as a very important source of delay variations in nanometer technologies.