Understanding middle-point inductance's effect on switching transients for multi-chip SiC package design with P-cell/N-cell concept

Abstract

Middle-point inductance L middle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying L middle . Extensive switching tests are conducted to evaluate the device's switching performance at different values of L middle . Experiment result shows that the active MOSFET's turn-on loss will decrease at higher values of L middle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. In addition to switching loss variation, it is also observed that different voltage stresses are imposed on the active switch and anti-parallel diode. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of lower MOSFET increases as L middle goes up; however, the peak voltage of anti-parallel diode decreases significantly. The analysis and experiment results will provide design guidelines for multiple-chip power module package design with P-cell/N-cell concept.