Understanding Clock Skew in Synchronous Systems

Abstract

Clock distribution and synchronization in synchronous systems are important issues especially as the size of the system and/or the clock rate increase. Minimization of clock skew has always been a major concern for the designers. Many factors contribute to clock synchronization and skew in a synchronous system. Among the major factors are: the clock distribution network, choice of clocking scheme, the underlying technology, the size of the system and level of integration, the type of material used in distributing the clock, clock buffers, and the clock rate. To be able to get around the problems related to clock skew and synchronization, one has to understand the effect that clock skew can have on the operation of a given system. In this paper we derive simple and practical formulations of these effects in terms of a few time-parameters that can be considered as properties of the individual modules and the clock network in a synchronous system. Knowing these time-parameters, one can determine the maximum throughput of a given system as well as its reaction to a change in clock skew. Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered. However, using the approaches discussed in this paper, the effect of clock skew for any other clocking scheme can be analyzed and formulated.