Abstract

With the current development of IC technology nodes becoming “Moore-than-Moore” challenging, industry and research institutes such as Imec are increasing their focus to come up with solutions to these challenges. A solution closely followed at the moment is the development of 3D ICs and 3D packaging. In developing these technologies, there are quite a lot of complexities involved. The development and scaling of TSVs and micro-bumps, the handling of ultra thinned wafers, the stacking options needed and the selection of the right type of underfill material are widely considered as main challenges for 3D IC technology. In this paper we report on the activities for underfill development. The underfill material is one of the most critical parts of standard flip chip package and will also be a critical component for 3D stacks and packages. The selection of the right material is fundamental to ensure the reliability and cost effectiveness of both the 3D stack and package. Currently most of the underfill materials for 3D stacking are still under development, it is therefore important to evaluate, screen and develop such materials. A close collaboration with industry partners, material vendors, equipment vendors and chip manufacturers (FAB and Packaging) will hasten the development of these materials. In this paper, we will show the underfill screening methodology used at Imec and the criteria used to judge the effectiveness of the materials. The report will mainly cover 2 types of underfill materials, namely, No Flow Underfills and Wafer Level Underfills. Both underfill materials can be applied on die or at wafer level. Reliability, electrical testing, SAM inspection and cross-section results will also be presented. The materials are ranked based on the criteria and results gathered for the DoEs performed. The lessons learned based on the materials' characteristics will be discussed and may be considered as guidelines for selecting a specific material a particular 3D stacks or packages.

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