Ultra-Wideband Low-Loss Switch Design in High-Resistivity Trap-Rich SOI With Enhanced Channel Mobility

Abstract

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- $\mu \text{m}$ high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( $L_{g} = 0.2~\mu \text{m}$ ) with low $R_{\mathrm{\scriptscriptstyle ON}} {^\ast} C_{\mathrm{\scriptscriptstyle OFF}}$ from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only $0.214 \times 0.19~\text {mm}^{2}$ and $0.36 \times 0.19~ \text {mm}^{2}$ , respectively.