Ultra-Thinning of 20 nm-Node DRAMs down to 3 µm for Wafer-on-Wafer (WOW) Applications

Abstract

Ultra-thinning of 20 nm-node DRAM wafers down to 3–5 µm was demonstrated for bumpless Wafer-on-Wafer (WOW) applications. Two different types of thinning process, namely, grinding (#2000 grit abrasive) and chemical mechanical polishing (CMP), were carried out in order to evaluate the relationship between device characteristics and the features of defects on the back side, as well as the influence of Cu contamination. No obvious degradation of the retention characteristics occurred even when the Si thickness was reduced to 3 µm, regardless of the thinning process used. The grinding-finished surface showed better gettering ability than that of CMP. The standby current increased by more than 15-times when the Si thickness was reduced to 4 µm by grinding, whereas the current increased by only 2.7-times in the case of CMP. This suggests that the standby current is strongly dependent on the thinning process. Probable degradation mechanisms are also discussed.