Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

Abstract

The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using test samples with quasi-through-hole electrodes. Application of chip-to-chip interconnection to a conventional 3D-stacked system-in-package (SiP) with an microprocessing unit (MPU) chip and an synchronous DRAM (SDRAM) chip reduced the package thickness to less than 0.5 mm from 1.25 mm and the number of layer in the package substrate to two (thickness less than 0.2 mm) from six (0.45 mm). The wiring distance between stacked chips is minimized by using an interposer chip. We formed through-hole electrodes in a 30-mum-thick silicon wafer and determined that the measured leakage with plasma CVD of SiO2 met our target specification for the electrical insulation between through-hole electrodes. Use of this method should facilitate the production of ultra-slim, high-performance SiP