Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates

Abstract

Supply-voltage reduction in digital circuits beyond the minimum energy per operation point is advantageous for supply-voltage-constrained applications and can help to considerably reduce standby power consumption. Schmitt trigger (ST) logic allows for ultra-low voltage (ULV) operation; hardware implementations with supply voltages as low as 62mV have been demonstrated. In this paper, a systematic in-depth analysis of ST logic is presented. First, it is shown that ST logic allows for operation at supply voltages below the ultimate limit of standard digital CMOS circuits, making it—to the best of our knowledge—the only approach proposed to date for operation of digital circuits in this voltage region. The factors critical to the ultimate limit of supply voltage reduction are the ON-to-OFF current ratio of the transistors and the susceptibility to global variability. It is shown that ST logic provides improvements over standard CMOS logic in both of these aspects. The hysteresis that occurs in ST circuits at nominal supply voltage could potentially limit the applicability for ULV operation and is therefore carefully investigated. Furthermore, a systematic approach to optimum sizing of ST gates is presented for the first time. ST gates exhibit inherent overheads with respect to gate area, delay, and leakage, which are carefully evaluated. Compared with standard CMOS gates designed for the same minimum supply voltage, it is shown that ST gates, nevertheless, are the most efficient solution if the target minimum supply voltage is sufficiently low: with respect to area, this limit is at $V_{DD}\approx 110\,mV$ and with respect to power/delay at $V_{DD}\approx 75\,mV$ .