Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing

Abstract

This paper presents the benefits of both co-implantation of diffusion-retarding species and ultra-fast annealing techniques as studied on blanket and device wafers. F and C co-implantation with B+ for PMOS and P+ for NMOS combined with conventional spike annealing produce reduced junction depths and improved dopant activation and profile abruptness, as measured on blanket wafers and compared to similar implants without the co-implanted species. Device wafers show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Depending on the implant conditions, either the gate/extension overlap capacitance or the series resistance can be improved when sub-melt laser annealing is used instead of conventional spike anneal. For both approaches, scanning spreading resistance microscopy (SSRM) measurements confirm the shallow junction depths and reduced lateral diffusion.