Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po-Yen Chiu Po-Yen Chiu,Yeong-Jar Chang Yeong-Jar Chang,Ming-Dou Ker Ming-Dou Ker,Fu-Yi Tsai Fu-Yi Tsai

doi:10.1109/irps.2009.5173343

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Po-Yen Chiu Po-Yen Chiu, Yeong-Jar Chang Yeong-Jar Chang + Show 2 more

https://doi.org/10.1109/irps.2009.5173343

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Publication Date: Apr 1, 2009

Citations: 16

Affiliation: National Yang Ming Chiao Tung University, I-Shou University, Faraday Technology (Taiwan)

#Power-rail ESD Clamp Circuit #MM ESD + Show 8 more

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Abstract

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116 nA at 25degC, which is much smaller than that (613 muA) of traditional design. Moreover, it can achieve ESD robustness of over 8 kV in HBM and 800 V in MM ESD tests, respectively.

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