Ultra-Low Specific On-Resistance Trench SOI LDMOS with a Floating Lateral Field Plate

Abstract

ABSTRACTAn ultra-low specific on-resistance (Ron,sp) trench silicon-on-insulator (SOI) LDMOS is proposed in this paper. In this novel structure, a floating lateral metal field plate (FLFP) is introduced into the oxide trench of the conventional SOI LDMOS (con-TLDMOS) and connected to the gate outside the device working region. The oxide trench causes multidirectional depletion, which leads to electric field reshaping. The FLFP causes an assistant depletion effect especially for the trench surface regions, which significantly increases the doping concentration of the drift region (Nd). Therefore, a novel structure (FLFP-TLDMOS) with a breakdown voltage (BV) of 188 V and an Ron,sp of 1.05 mΩ·cm2 is obtained on a 4.8-μm-long drift region. Compared with the con-TLDMOS, the Ron,sp of the FLFP-TLDMOS can be reduced by about 54.3%; furthermore, its BV is maintained the same class with the con-TLDMOS, and the figure of merit is increased by 118%. Furthermore, the dynamic performance and self-heating effect of the novel structure are slightly improved compared with the conventional trench structure.