Abstract
The design considerations and circuit topologies of a family of ultralow-power fundamental-frequency and second-harmonic 60-GHz radar sensors are described. The single-chip sensor architecture features four low-noise-matched receivers, either a fundamental-frequency 60-GHz voltage-controlled oscillator (VCO) or 30-GHz VCO + doubler, and a static divide-by-8192 chain which is turned OFF 95% of the time to save DC power. On-die measurements show a power consumption of 42 mW from a single 1.2-V supply, 10% frequency tuning range, −104 to −108 dBc/Hz phase noise at 10-MHz offset, 10-dB conversion gain per receiver, and −7-dBm transmitter output power at the antenna pads. Several 45-nm SOI-CMOS sensor dies were flip-chip mounted on a $7\times 7$ mm2 flexible interposer which also includes four receive- and two transmit antennas. Doppler and direction of arrival tests were conducted over distances of several tens of centimeters.
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