Ultra-low power NAND based multiplexer and flip-flop

Abstract

Static power consumption has became a major problem as we are moving towards finer technologies. Power consumption is one of the top concerns of VLSI circuit design, for which CMOS is the primary technology. However, there is no universal way to avoid tradeoffs between power, delay and area, and thus designers are required to choose appropriate techniques that satisfy application and product needs. We are presenting two low power digital circuits 4*1 multiplexer and JK master-slave flip-flop designed with ultra low power NAND gates. These NAND gates have been designed with combination of sleepy stack technique with reverse body bias (RBB) and dual threshold CMOS (DTCMOS). On comparison with conventional 4*1 multiplexer we have achieved maximum of 30% decrement in dynamic power consumption and 59% decrement in power consumption when circuit is in ideal state. This all is achieved on the coast of 55% increment in worst case propagation delay. For JK master-slave flip-flop we are achieving 13% reduction in dynamic power consumption and 99% saving in static power consumption. All simulations have been done on 65nm technology with dual threshold transistors.