Ultra-low power and robust analog computing circuits and system design framework for machine learning applications

Abstract

As the scaling of CMOS transistors has almost halted, performance gains of digital systems have also started to stagnate. There is a renewed interest in alternate computing techniques such as in-memory computing, hybrid computing, approximate computing, and analog computing. In particular, analog computing has reemerged as a promising alternative to save power and improve performance specifically for machine-learning (ML) applications. Power and chip area efficiency make analog computing highly appealing for implementing deep learning algorithms on-chip, computing circuits for the internet-of-things (IoT) devices, and implantable and wearable biomedical devices. However, compared to digital computing, analog computing methods have not nearly been utilized to their fullest potential due to longstanding challenges related to reliability, programmability, power consumption, and high susceptibility to variations. The subject of this dissertation research is to develop robust ultra-low power analog hardware suitable for machine learning applications. First, a robust analog design methodology is presented to address issues of variability in analog circuits. A constant transconductance design technique using switched capacitor circuits is presented. The design approach is then applied to build circuits for ML applications. An analog vector matrix multiplier (VMM) is designed to be used in the convolutional layer in an ML analog computing vision hardware platform. Computing circuits are tested as part of an image classification DNN algorithm on the MNIST dataset and can achieve a classification accuracy of 96.1%. The design approach is also used to design an analog computing system architecture for detection of seizures using EEG signals. A conventional EEG monitoring system includes an analog front-end (AFE), ADC, digital filtering stage, EEG feature extraction engine, and SVM classification. Such systems suffer from high power and chip area requirements. The corresponding analog architecture is composed of AFE amplifiers to provide gain for the incoming signal. The AFE is followed by an analog filtering stage, where spectral power from each of the bands is used as a feature for seizure classification. The output of each filter is applied to a corresponding feature extraction circuit to continuously monitor the onset of a seizure in an ultra-lower power mode with sub-threshold analog processing. The system level architecture is first modeled to obtain classification accuracy of seizures. Simulation times for the design of such complex analog systems can be prohibitively long, particularly when the impacts of nonidealities such as noise, nonlinearity, and device mismatches have to be considered at the system level. The simulation time is reduced by building accurate models of the analog blocks for faster simulations. The analog models help to define the required specifications for each block in order to achieve a specified system-level classification accuracy. Infrastructure circuits like oscillators and voltage regulators for the proposed SoC are presented. A 254 nW 21 kHz on-chip RC oscillator with 21.5 ppm/◦C temperature stability is presented to provide stable clock source for the proposed SoC. Finally, novel lightweight hardware security primitives are described to equip individual IoT devices with side-channel resistant crypto-implementations, and unique ID or key generation. We describe a switched capacitor converter resilient to side channel power attacks, achieving a high efficiency of 77%. We also describe a low power, low area weak physically unclonable function with 7.5fJ/bit energy efficiency. --Author's abstract