Ultra-low phase noise 76–81 GHz PLL synthesizer for FMCW radar in 65 nm CMOS

Abstract

A fully-integrated 79-GHz phase-locked loop (PLL) synthesizer for ultra wideband (UWB) frequency-modulated continuous-wave (FMCW) radar which has ultra-low phase noise is presented. The PLL includes an on-chip isolation transformer to distribute the RF signal. Moreover, the negative resistance amplifier for the reference oscillator and the on-chip loop filter are integrated. This PLL with a 49-MHz crystal oscillator exhibits a low phase noise of −84.2 dBc/Hz at 100 kHz offset and −84.9 dBc/Hz at 1 MHz offset. It consumes 253 mW of power from a 1.2 V supply voltage. Also, a lower phase noise of −92.8 dBc/Hz at 100 kHz offset and −98.9 dBc/Hz at 1 MHz offset is achieved when the 294 MHz surface acoustic wave (SAW) oscillator is used as a reference. It employs a fractional PLL architecture for frequency synthesis. The output frequency is modulated by a digital circuit with a 28-bit 3rd order delta-sigma modulator. An ultra-wide modulation width of 5-GHz, from 76 to 81 GHz, is achieved. To the best of the authors' knowledge, this circuit has the lowest phase noise in W-band CMOS PLL synthesizers. This is also the first PLL synthesizer which is applicable for UWB FMCW radar.