Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet

Abstract

Key-value store (KVS) systems are playing important roles as the caches of database to improve the data access efficiency. In this paper, we propose general architectures of KVS systems based on field programmable gate arrays (FPGAs) which can adapt to different application scenarios. Data hazards introduced by the pipeline are fully handled to improve the throughput. The batch operation is proposed to support the variable-length key-value pairs. The memory address management system reduces CPU load further by managing memory addresses on hardware. We implement and evaluate our KVS systems on VC709 evaluation board targeting throughput, latency and capacity respectively. The ultra-low latency KVS system can achieve 160 ns latency and about 155 million request per second (MRPS) to retrieve 96-bit values with 96-bit keys. The ultra-high throughput KVS system can achieve about 200 ns latency and 200 MRPS throughput to retrieve the same size key-value pairs. The ultra-capacity KVS system retrieves 64-byte values with 12-byte keys, serving a maximum request rate of more than 35 MRPS with latency less than 500 ns.